Non-volatile memory cell with a hybrid access transistor

ABSTRACT

An integrated circuit (IC) is disclosed. The IC comprises a substrate with a cell region defined thereon. The cell region comprises a thin gate doped well tailored for transistors with thin gate dielectric layers. The IC also includes a non-volatile memory cell in the cell region. The non-volatile memory cell has an access transistor and a storage transistor. The access transistor includes an access gate with an access gate dielectric comprising a thick gate dielectric layer on the thin gate doped well. Wells for transistors with thick gate dielectric layers have a lower dopant concentration than the thin gate doped well.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application which claims benefit ofcopending U.S. patent application Ser. No. 11/740,939, filed on Apr. 27,2007. All disclosures are incorporated herewith by reference.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits (ICs),and more particularly to non-volatile memory devices.

BACKGROUND OF THE INVENTION

Non-volatile memory devices are able to retain stored data even when thepower supply is interrupted. Non-volatile memory devices comprise flashdevices which can be programmed using electrical signals. For the memorydevice to be byte-operational, a 2T cell structure consisting of amemory transistor and a select or access transistor in series can beprovided. The memory transistor stores data programmed into the memorycell, while the access transistor selects the memory cell to beprogrammed or erased.

The memory transistor can be of various types including, for example,floating gate type, metal-nitride-oxide-silicon (MNOS) type,silicon-nitride-oxide-silicon (SNOS) type,metal-oxide-nitride-oxide-silicon (MONOS) type, andsilicon-oxide-nitride-oxide-silicon (SONOS) type. The SONOS type memorytransistor has a stacked gate structure comprising a nitride layersandwiched between lower and upper oxide layers, and a polysilicon gatelayer. The lower oxide layer is a tunnel oxide layer, the nitride layeris a memory or storage layer, and the upper oxide layer is a blockinglayer for preventing the loss of stored charge. The charge-trappingability of the SONOS stack structure allows lower programming and erasevoltages to be used. The SONOS memory transistor also comprises sourceand drain regions formed on either side of the stack structure.

Programming is typically by hot carrier injection. Programming speeddepends on the efficiency of hot carrier generation which, in turn,depends on the programming current. Programming current is affected byvarious factors including, for example, channel doping level and gatewidth of the memory transistor. Erase can be by Fowler-Nordheim (F-N)tunneling.

Generally, it is desirable to provide a non-volatile memory devicehaving high programming speed and small cell size to allow for highdensity memories.

SUMMARY OF THE INVENTION

An integrated circuit (IC) is disclosed. The IC includes a substratewith a cell region defined thereon. The cell region comprises a thingate doped well tailored for transistors with thin gate dielectriclayers. A non-volatile memory cell in the cell region is also included.The non-volatile memory cell has an access transistor and a storagetransistor. The access transistor includes an access gate with an accessgate dielectric comprising a thick gate dielectric layer on the thingate doped well. Wells for transistors with thick gate dielectric layershave a lower dopant concentration than the thin gate doped well.

Another device is also presented. The device includes a substrate withan active region prepared with a thin gate doped cell well tailored fortransistors with thin gate dielectric. A transistor is also included inthe active region on the thin gate doped well. The transistor comprisesa gate having a gate electrode over a thick gate dielectric.

In yet another embodiment, a device is disclosed. The device includes asubstrate with a cell region defined thereon. The cell region comprisesa thin gate doped well tailored for transistors with thin gatedielectric layers. First and second transistors are disposed in the cellregion. The first transistor includes a first gate with a first gatedielectric comprising a thick gate dielectric layer on the thin gatedoped well.

These and other objects, along with advantages and features of thepresent invention herein disclosed, will become apparent throughreference to the following description and the accompanying drawings.Furthermore, it is to be understood that the features of the variousembodiments described herein are not mutually exclusive and can exist invarious combinations and permutations.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the sameparts throughout the different views. Also, the drawings are notnecessarily to scale, emphasis instead generally being placed uponillustrating the principles of the invention. Various embodiments of thepresent invention are described with reference to the followingdrawings, in which:

FIG. 1 shows a non-volatile memory cell in accordance with oneembodiment of the invention;

FIG. 2 shows a non-volatile memory array in accordance with oneembodiment of the invention;

FIG. 3 shows a cross-sectional view of a non-volatile memory cell inaccordance with one embodiment of the invention;

FIG. 4 shows gate voltage-drain current (V_(g)-I_(d)) curves of thehybrid access transistor according to one embodiment of the invention;and

FIGS. 5 a-j show a process flow for forming an IC in accordance with oneembodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to non-volatile memory cells. Moreparticularly, the present invention relates to a 2T flash typenon-volatile memory device which increases programming speed whilereducing cell size, enabling high density memories to be fabricated. Thenon-volatile memory cells can be incorporated into ICs and easilyintegrated into current CMOS processing technologies. The ICs can be anytype of IC, for example non-volatile memories, signal processors, orsystem on chip devices. Other types of ICs are also useful. Such ICs areincorporated in, for example, microcontrollers, communication systems,consumer products such as cell phones and memory cards.

FIG. 1 shows a non-volatile memory cell 110 in accordance with oneembodiment of the invention. As shown, the memory cell comprises firstand second series coupled transistors 120 and 140. The first transistorserves as an access transistor and the second transistor serves as astorage transistor. The transistors, in one embodiment, comprisetransistors of a first polarity type. For example, the transistorscomprise p-type transistors. N-type transistors are also useful.Alternatively, both n and p-type transistors are used. The firsttransistor includes a gate terminal 125 and first and second terminals122 and 123; the second transistor includes a gate terminal 145 andfirst and second terminals 142 and 143. The gate terminal of the firsttransistor is coupled to an access gate line (AG) while the gateterminal of the second transistor is coupled to a control gate line(CG). The second terminals of the transistors are commonly coupled.Source and bit lines, SL and BL, are respectively coupled to the firstterminals of the access and storage transistors.

In accordance with one embodiment of the invention, the accesstransistor comprises a hybrid transistor. The hybrid transistor includesa thick gate oxide 128 with a doped well 115 to accommodate a transistorwith a thin gate oxide. The doped well comprises second polarity typedopants. For example, the doped well comprises a n-well for p-typetransistors. As for the storage transistor, it includes a compositecharge storing layer 148. In one embodiment, the composite chargestorage layer comprises an oxide-nitride-oxide (ONO) stack. Other typesof storage layers, such as nanocrystal embedded in oxide andoxide-metal(high-K)-oxide stack are also useful.

As shown in FIG. 2, a plurality of memory cells 110 can be provided toform a memory array 205. As shown, the memory cells are interconnectedby control gate lines 280 _(1-i), access gate lines 282 _(1-i), bitlines 286 _(1-i), and source lines 288 _(1-i). Generally, the controland access gate lines are arranged in a first direction while the sourceand bit lines are arranged in a second direction. Other configurationsare also useful. Logic circuitry (not shown) can be included to programand access the memory array.

FIG. 3 shows a cross-sectional view of a memory cell 310 in accordancewith one embodiment of the invention. The memory cell is formed on asubstrate 311. The substrate, for example, comprises a lightly dopedp-type silicon substrate. Other types of substrates are also useful. Thesubstrate includes a cell region 306 for the memory cell. Isolationregions (not shown) are provided to isolate the cell region from othercells or devices. The isolation regions comprise, for example, shallowtrench isolation regions. Other types of isolations are also useful.Typically, numerous cell regions are provided in an array region on asubstrate. Logic devices, such as input/output (I/O) circuitry andcontrol circuitry can be provided in a peripheral or logic region (notshown) on the substrate.

The cell region includes first and second transistors 320 and 340, withthe first transistor serving as an access transistor and the secondtransistor serving as a storage transistor. The transistors, in oneembodiment, comprise transistors of a first polarity type. In oneembodiment, the transistors comprise p-type transistors. N-typetransistors are also useful. Each transistor includes first and seconddiffusion regions (322, 323, 342, 343) adjacent to a gate stack (325,345). The diffusion regions are formed by first polarity type dopants.Preferably, the transistors share a common second diffusion region323/343. Contacts, such as silicide contacts, can be provided for thediffusion regions. A doped well 315 is provided beneath the substrate inthe cell region. The doped well comprises a second polarity type dopedwell.

Disposed on the substrate in the cell region is the gate stack of theaccess transistor. The gate stack includes a gate layer 327 over a gatedielectric layer 328. The gate layer comprises, for example,polysilicon. As for the gate dielectric layer, it can comprise varioustypes of dielectric materials. Preferably, the gate dielectric comprisesthermal oxide. In one embodiment, the gate dielectric layer comprises athick gate dielectric layer, with a physical thickness typically about30-80 Å. Other thicknesses may also be useful. In accordance with oneembodiment of the invention, the doped well on which the accesstransistor is formed comprises a doped well tailored for a transistorwith a thin gate dielectric layer (thin gate well), providing a hybridaccess transistor. The thin gate doped well, for example, comprises adopant concentration of about E17-E19 cm⁻³, and a depth of about 0.7-1.4μm. Other concentrations and depths are also useful.

On the surface of the substrate in the cell region over the doped wellis also disposed the gate stack of the storage transistor. Preferablyboth the access and storage transistors are formed in the same well.Forming the transistors in a common well region enables the memory cellto be reduced in size. The gate stack comprises a gate layer 347 over astorage dielectric layer 348. Typically, the gate layer comprisespolysilicon. Other types of materials can also be used to form the gatelayer.

In one embodiment, the storage layer comprises an oxide-nitride-oxide(ONO) trilayer, forming a SONOS gate stack structure. The ONO trilayerincludes a lower (tunneling) oxide layer 331, an upper (blocking) oxidelayer 333, and a nitride layer 332 sandwiched therebetween. Otherdielectric materials capable of storing electrical charges may also beused. Additionally, the storage layer may comprise one, two or morelayers. For example, a bilayer storage layer comprising a nitride layerand a tunneling oxide layer can be used. To facilitate tunneling andtrapping of electrical charges for efficient programming and erasing ofthe non-volatile memory, the lower oxide layer is preferably about 24-45Å physically thick, the nitride layer is preferably about 40-80 Å thick,and the upper oxide layer is preferably about 40-80 Å thick. Morepreferably, the lower oxide layer, nitride layer, and upper oxide layerare, respectively, about 35 Å, 45 Å and 45 Å thick. Other types of flashmemories can also be used.

Although not shown, an interlevel dielectric layer is provided over thememory cell. Contacts are provided, coupling the diffusion regions andgate electrodes to source lines, bit lines, access gate lines andcontrol gate lines.

As described, a non-volatile memory cell includes a hybrid accesstransistor with a thick gate dielectric layer formed on a thin gatewell. Thin gate wells have higher channel doping compared to thick gatewells (wells tailored for transistors with thick gate dielectriclayers), resulting in higher carrier generation efficiency. Furthermore,the thick gate dielectric layer of the hybrid access transistor allowshigher bias voltages to be used. Higher bias voltages result inincreased programming currents, which improve programming speed.

Preferably, the gate length of the storage transistor is reduced toincrease tunneling current for higher programming speed. Furthermore,the gate length of the access transistor is reduced to be the thin gatechannel length, resulting in smaller memory cell sizes. The gates,however, must be of sufficient length to prevent punch-through. Sinceimmunity to punch-through increases with increased channel dopingconcentration, the use of thin gate wells allows transistors to havesmaller gate lengths than thick gate wells. The gate lengths of thetransistors, in a preferred embodiment, are selected to be at theminimum critical dimension (CD) for a specific process. More preferably,the minimum CD of each type of transistor is used. For example, for 0.18μm technology, the gate length of the access transistor is about 0.18 μmwhile that of the storage transistor is about 0.17 μm.

The memory cell can operate in various modes, such as programming,reading and erase modes. The erase mode is initiated by applyingappropriate bias conditions. In one embodiment, the erase mode isinitiated by applying about 3.3 V to the gate of the access transistor,about 6 V to the thin gate n-well, and about −6.25 V to the gate of thestorage transistor. Under such bias condition, data erasing is performedusing a F-N tunneling current that flows through the tunneling oxide,drawing electrons from the ONO stack of the non-volatile memorytransistor to the channel region. The bias voltage (V_(gb)) duringerase, which is equal to the difference between the access transistoroperating voltage and the n-well voltage, is about −2.7 V. Operation inthis low V_(gb) region avoids the problems of oxide breakdown, trap-upor transistor degradation associated with high electric field stressing.

The use of a thick gate oxide in the access transistor allows the accesstransistor to operate at 3.3 V. Conversely, if a thin gate oxide wereused, the access transistor can only operate at a maximum of 1.8 V ifgate oxide rupture is to be avoided. In such case, V_(gb) is about −4.2V in the erase mode since 6 V is applied to the thin gate n-well. Such ahigh bias voltage is liable to cause gate breakdown and reliabilityproblems. Accordingly, the use of a hybrid access transistor is thusable to provide favorable bias conditions.

FIG. 4 shows measured gate voltage-drain current (V_(g)-I_(d)) curves ofthe hybrid access transistor according to one embodiment of theinvention. The width, gate length, and gate oxide physical thickness ofthe transistor are 0.42 μm, 0.18 μm and 53 Å, respectively. V_(g)-I_(d)curves at different thick gate bias voltage (V_(gs)) values are shown.As shown, the hybrid transistor works normally at a gate bias of −3.3 V,where 3.3 V is a standard I/O voltage for 0.18 μm 1.8/3.3 V dual gateprocess technology. Thus, the hybrid transistor can be used as a thickgate transistor even if the well beneath is a thin gate well and gatelength is a thin gate channel length.

FIGS. 5 a-j illustrate an exemplary process flow for forming an IC 500in accordance with one embodiment of the invention. Referring to FIG. 5a, a substrate 511 is provided. The substrate comprises a semiconductorsubstrate, such as silicon. Other types of semiconductor substrates, forexample, SiGe, SiGeC, SiC, silicon-on-insulators (SOIs),SiGe-on-insulators (SGOIs), are also useful. In one embodiment, thesubstrate comprises a lightly doped p-type substrate. As shown, a cellregion 506 is provided on the substrate on which a memory cell isformed. The cell region, for example, is a part of an array region witha plurality of cell regions on which memory cells are formed to create amemory array. Typically, the substrate also includes a logic region (notshown) on which logic circuitry is formed.

The substrate is prepared with a doped well 515 in the cell region. Thedoped well comprises dopants of the second polarity type. The secondpolarity type, for example, comprises n-type, forming a n-well.Alternatively, the second polarity type comprises p-type. In accordancewith one embodiment of the invention, the doped well comprises a thingate well having a channel doping concentration of about E17-E19 cm⁻¹.Conventional ion implantation techniques, such as implantation with amask can be used to form the wells. Generally, the substrate includesfirst and second type wells in the logic region to form, for example,CMOS devices. Separate ion implantation processes are used for differenttypes of wells. The doped well in the cell region can be formed alongwith the same type of wells in the logic regions. Threshold voltage(V_(T)) implants are performed after well formation.

Isolation regions (not shown), such as STIs, are provided to isolate thecell region from other device regions. The STIs can be formed before orafter the well is formed. In one embodiment, the STIs are formed beforethe wells are formed.

Referring to FIG. 5 b, a storage layer is formed on the substratesurface. Typically, the storage layer is formed as a blanket layer onthe substrate, covering both the array and logic regions. The storagelayer, in one embodiment, comprises a composite layer stack. In oneembodiment, the composite layer stack comprises an oxide-nitride-oxide(ONO) stack 548. Other types of storage layers are also useful.Conventional techniques can be used to form the ONO stack. In oneembodiment, a tunneling oxide layer 531 is first formed. The tunnelingoxide layer can be formed by, for example, rapid thermal oxidation(RTO). Other techniques including, for example, low pressure chemicalvapor deposition (LPCVD) and thermal oxidation are also useful. Thephysical thickness of the tunneling oxide layer can be about 24-45 Å,and preferably about 35 Å. Next, a nitride layer 532 is deposited. Thethickness of the nitride layer can be about 40-80 Å, and preferablyabout 45 Å. The nitride layer can be formed by LPCVD or nitridation.Other techniques are also useful. Finally, the top or barrier oxidelayer 533 is formed. The thickness of the barrier oxide layer is about40-80 Å, and preferably about 45 Å. The barrier oxide layer may beformed using the same techniques as for the tunneling oxide layer.

Referring to FIG. 5 c, a photoresist layer 572 is deposited on thesubstrate. As is well known in the art, an anti-reflective coating (ARC)layer can be provided under the photoresist layer. For purposes of thisdiscussion, reference to photoresist or resist can include an ARC layer.Furthermore, removal of the photoresist or resist can include removal ofthe ARC layer. However, it is understood that in certain applications,the ARC layer can remain when the photoresist is removed. Thephotoresist layer is patterned to expose portions of the storage layerwhich are to be removed. At least the portion of the storage layer inthe cell region where the access transistor is formed is exposed.Additionally, portions of the storage layer in the logic region are alsoexposed. The exposed portions of the storage layer are removed, as shownin FIG. 5 d. Removal can be achieved using, for example, an anisotropicetch such as reactive ion etch (RIE). The etch preferably is selectiveto the substrate. As shown in FIG. 5 e, the photoresist layer is removedafter etch.

Referring to FIG. 5 f, a thick gate dielectric layer 528 is formed onthe substrate. The thick gate dielectric layer comprises, for example,silicon oxide. Other types of dielectric materials may also be useful.Preferably, the gate dielectric layer is formed by thermal oxidation orRTO. Thermal oxidation or RTO selectively forms the gate oxide on theexposed substrate. This is because in the storage transistor region, thethick gate oxide will not be formed since ONO trilayer serves as a hardmask. The physical thickness of the thick gate oxide is about 30-80 Å,and preferably about 46-60 Å. Other thicknesses may also be useful.Since the logic region is also exposed, the thick gate dielectric layeris also formed in the logic region.

In one embodiment, the array region is masked off for processing of thelogic region. For example, portions of the storage layer in the logicregion are removed, if applicable, and conventional dual gate processesare performed therein. For example, a thin gate dielectric layer isformed in the logic region. Since the array region is covered by masklayer during these processes, concerns about overlay or gate integrityissues are eliminated. Dual gate processes are described in, forexample, U.S. Pat. No. 7,029,976, which is incorporated herein byreference.

Referring to FIG. 5 g, a gate layer 538 is formed on the substrate. Thegate layer, for example, comprises a blanket gate layer on the substratewhich covers both the array and logic regions. In one embodiment, thegate layer comprises a polysilicon gate layer. The polysilicon gatelayer can be formed by chemical vapor deposition (CVD). The polysiliconlayer may be doped to impart a higher conductivity to the gate. Othermaterials including, for example, metal or polycide, may also be used inthe gate layer. The thickness of the polysilicon gate layer is, forexample, about 1800-2200 Å.

Referring to FIG. 5 h, the polysilicon gate layer and the layers beneathit are patterned to form gate stacks of the access and storagetransistors in the cell region. Gate stacks in the logic regions canalso be patterned along with the gate stacks in the cell region.Conventional patterning techniques can be used to form the gate stacks.For example, a photoresist layer 574 is deposited on top of thepolysilicon gate layer. The photoresist layer is patterned to exposeportions of the polysilicon layer. The exposed polysilicon gate layerand the layers beneath it are removed to form the first and second gatestacks 525 and 545, as shown in FIG. 5 i. Removal can be achieved using,for example, an anisotropic etch such as RIE. The etch is preferablyselective to the substrate. The remaining portions of the photoresistlayer on the top of the gate stacks are removed after etching.

Referring to FIG. 5 j, first and second diffusion regions (522, 523,542, 543) of the first polarity type are formed on the substrateadjacent to the gate stacks, creating first polarity type transistors.The diffusion regions comprise doped regions in the well. The firstpolarity type, for example, comprises p-type, resulting in p-typediffusion regions in the n-well. In one embodiment, the transistorsshare a common second diffusion region 523/543 located between the gatestacks. The diffusion regions, for example, are formed usingconventional techniques, such as ion implantation. Generally, first andsecond type diffusion regions are formed in the logic region. In oneembodiment, the diffusion regions in the array region can be formedalong with the first type diffusion regions in the logic region.

The process continues by forming interconnections to the diffusionregions and gates of the transistors. For example, the diffusion regionsand gates are appropriately coupled to source lines, bit lines, accesslines and control lines. Additionally, the thin gate well is coupled toa bias voltage. Appropriate interconnections are also formed in thelogic region. Additional processes are performed to complete the IC.These processes include, for example, final passivation, dicing, andpackaging.

As described, the memory cell of the present invention can be easilyintegrated into conventional CMOS processes. By forming and patterningthe thick gate dielectric layer in the logic and cell regionsconcurrently, the additional gate steps are reduced or minimized. Noadditional implant processes are required to form the hybrid accesstransistors. By providing a memory cell design which facilitates simplecircuit routing along with minimum CD gate lengths, cell size is reducedand density is increased. Furthermore, masking off the array regionduring dual gate processes eliminates overlay or gate integrity issuesin the array region. In addition, the thick gate oxide of the accesstransistor allows for appropriate bias conditions to increaseprogramming speed reliably. Therefore, the present invention provides asimple, reliable, high performing and low cost solution for integratingnon-volatile memories in ICs.

The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The foregoingembodiments, therefore, are to be considered in all respectsillustrative rather than limiting the invention described herein. Scopeof the invention is thus indicated by the appended claims, rather thanby the foregoing description, and all changes that come within themeaning and range of equivalency of the claims are intended to beembraced therein.

1. An integrated circuit (IC) comprising: a substrate with a cell regiondefined thereon, the cell region comprises a thin gate doped welltailored for transistors with thin gate dielectric layers; and anon-volatile memory cell in the cell region, the non-volatile memorycell having an access transistor and a storage transistor, wherein theaccess transistor includes an access gate with an access gate dielectriccomprising a thick gate dielectric layer on the thin gate doped well,wherein wells for transistors with thick gate dielectric layers have alower dopant concentration than the thin gate doped well.
 2. The IC ofclaim 1 wherein the storage transistor comprises: a storage gate in astorage portion of the cell region, the storage gate comprises a storagelayer and a storage gate electrode over the storage layer; and first andsecond storage diffusion regions adjacent to the storage gate.
 3. The ICof claim 1 wherein the access transistor comprises: the access gatecomprising the access gate dielectric and an access gate electrode overthe thick gate dielectric layer; and first and second access diffusionregions adjacent to the access gate.
 4. The IC of claim 1 wherein thememory cell comprises: a storage layer in a storage portion of the cellregion; the access gate dielectric in an access portion of the cellregion; and a gate electrode layer over the storage layer and thick gatedielectric layer.
 5. The IC of claim 4 wherein the memory cell comprisesa storage gate and the access gate over the cell region, wherein thestorage gate comprises a gate electrode formed from patterning the gateelectrode layer over the storage layer and the access gate comprises anaccess gate electrode formed from patterning the gate electrode layerover the access gate dielectric.
 6. The IC of claim 5 comprises firstand second access diffusion regions adjacent to the access gate andfirst and second storage diffusion regions adjacent to the storage gate.7. The IC of claim 6 includes a common diffusion region comprising oneof the access diffusion regions is adjacent to the storage gate and oneof the storage diffusion regions is adjacent to the access gate.
 8. TheIC of claim 4 wherein the storage layer comprises a composite storagelayer.
 9. The IC of claim 4 wherein the storage layer comprises acomposite storage layer comprising an oxide-nitride-oxide stack.
 10. TheIC of claim 1 wherein: the thin gate doped well comprises n-type dopantsand the transistors comprise p-type transistors; or the thin gate dopedwell comprises p-type dopants and the transistors comprise n-typetransistors.
 11. The IC of claim 1 wherein the thin gate doped wellcomprises a dopant concentration of about E17-E19 cm⁻³.
 12. The IC ofclaim 1 wherein the thick access gate dielectric is about 30-80 Å thick.13. A device comprising: a substrate with an active region prepared witha thin gate doped cell well tailored for transistors with thin gatedielectric; and a transistor in the active region on the thin gate dopedwell, wherein the transistor comprises a gate having a gate electrodeover a thick gate dielectric.
 14. The device of claim 13 wherein: thethin gate doped well comprises n-type dopants and the transistorcomprises a p-type transistor; or the thin gate doped well comprisesp-type dopants and the transistor comprises a n-type transistor.
 15. Thedevice of claim 13 wherein the thin gate doped well comprises a dopantconcentration of about E17-E19 cm⁻³.
 16. The device of claim 13 whereinthe active region comprises a cell region of a memory cell.
 17. Thedevice of claim 16 wherein the memory cell comprises: an accesstransistor having an access gate electrode over a thick access gatedielectric; and a storage transistor coupled to the access transistor,the storage transistor having a storage gate electrode over a storagegate dielectric.
 18. The device of claim 17 wherein the storage gatedielectric comprises an ONO storage stack.
 19. The device of claim 17wherein the thick access gate dielectric is about 30-80 Å thick.
 20. Adevice comprising: a substrate with a cell region defined thereon, thecell region comprises a thin gate doped well tailored for transistorswith thin gate dielectric layers; and first and second transistorsdisposed in the cell region, wherein the first transistor includes afirst gate with a first gate dielectric comprising a thick gatedielectric layer on the thin gate doped well.
 21. The device of claim 20wherein the cell region comprises a memory cell.
 22. The device of claim20 wherein: the thin gate doped well comprises n-type dopants and thetransistors comprise p-type transistors; or the thin gate doped wellcomprises p-type dopants and the transistors comprise n-typetransistors.
 23. The device of claim 20 wherein: the first transistorcomprises an access transistor having an access gate electrode over thefirst thick gate dielectric; and the second transistor comprises astorage transistor coupled to the access transistor, the storagetransistor having a storage gate electrode over a storage gatedielectric.
 24. The device of claim 20 wherein the thin gate doped wellcomprises a dopant concentration of about E17-E19 cm⁻³.
 25. The deviceof claim 23 wherein the storage gate dielectric comprises a compositestorage layer.